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RF1K49157
Data Sheet August 1999 File Number
4012.5
6.3A, 30V, 0.030 Ohm, Single N-Channel LittleFETTM Power MOSFET
This Single N-Channel power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching convertors, motor drivers, relay drivers, and low voltage bus switches. This device can be operated directly from integrated circuits. Formerly developmental type TA49157.
Features
* 6.3A, 30V * rDS(ON) = 0.030 * Temperature Compensating PSPICETM Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
NC (1) DRAIN (8)
Ordering Information
PART NUMBER RF1K49157 PACKAGE MS-012AA BRAND RF1K49157
SOURCE (2) DRAIN (7)
NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4915796.
SOURCE (3) DRAIN (6)
GATE (4)
DRAIN (5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5 1 2 3 4
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. LittleFETTM is a trademark of Intersil Corporation. PSPICETM is a trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RF1K49157
Absolute Maximum Ratings
TA = 25oC Unless Otherwise Specified RF1K49157 30 30 20 6.3 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse width = 1s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation TA = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 12) VGS = VDS, ID = 250A, (Figure 11) VDS = 30V, VGS = 0V VGS = 20V ID = 6.3A (Figures 9, 10) VGS = 10V VGS = 4.5V TA = 25oC TA = 150oC MIN 30 1 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 24V, ID = 6.3A, RL = 3.81 (Figure 14) Pulse width = 1s Device mounted on FR-4 material TYP 22 43 125 85 70 38 2.8 1575 700 200 MAX 3 1 50 100 0.030 0.060 85 265 88 48 3.5 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance
IGSS rDS(ON)
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction-to-Ambient
tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJA
VDD = 15V, ID 6.3A, RL = 2.38, VGS = 10V, RGS = 25
VDS = 25V, VGS = 0V, f = 1MHz (Figure 13)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 6.3A ISD = 6.3A, dISD/dt = 100A/s MIN TYP MAX 1.25 60 UNITS V ns
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RF1K49157 Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 0.8 7 6 5 4 3 2 1 0 25
0.6 0.4
0.2 0
50 75 100 125 TA, AMBIENT TEMPERATURE (oC)
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
10
ZJA, NORMALIZED THERMAL IMPEDANCE
1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 102 103 PDM
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
IDM, PEAK CURRENT CAPABILITY (A)
TJ = MAX RATED, TA = 25oC
300
VGS = 20V VGS = 10V
TA = 25oC
ID, DRAIN CURRENT (A)
100
10
1
5ms 10ms 100ms
10
THERMAL IMPEDANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.01 0.1 1s VDSS(MAX) = 30V DC 100
= I25
10-4
1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
1 10-5
150 - TA 125 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RF1K49157 Typical Performance Curves
50 IAS, AVALANCHE CURRENT (A)
(Continued)
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] ID, DRAIN CURRENT (A)
50
40
VGS = 20V VGS = 10V VGS = 7V VGS = 5V
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC
10
STARTING TJ = 25oC
30 VGS = 4V 20
STARTING TJ = 150oC 1 0.1
10
1 10 tAV, TIME IN AVALANCHE (ms)
100
0
0
1
2
3
4
5
NOTE:
Refer to Intersil Application Notes AN9321 and AN9322.
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
50 ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40
150oC
rDS(ON), ON-STATE RESISTANCE (m)
-55oC
25oC
VDD = 15V
250 ID = 15A 200 ID = 6.3A ID = 3.5A ID = 1.75A
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
30
150
20
100
10
50
0 0
1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V)
7.5
0
2
8 6 4 VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
2.0 NORMALIZED ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 6.3A NORMALIZED GATE THRESHOLD VOLTAGE 1.5
2.0 VGS = VDS, ID = 250A 1.5
1.0
1.0
0.5
0.5
0 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
0 -80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
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RF1K49157 Typical Performance Curves
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 2000 C, CAPACITANCE (pF) 1.5 CISS 1500
(Continued)
2500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
1.0
1000 COSS 500
0.5
CRSS
0 -80
-40
0 40 80 120 TJ , JUNCTION TEMPERATURE (oC)
160
0
0
5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
30 VDS , DRAIN-SOURCE VOLTAGE (V)
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10.0 VGS , GATE-SOURCE VOLTAGE (V)
22.5 VDD = BVDSS 15 RL = 4.76 IG(REF) = 0.8mA VGS = 10V PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS
7.5
5.0
7.5
2.5
0
0 I G ( REF )
20 --------------------I G ( ACT )
I G ( REF )
t, TIME (s)
80 --------------------I G ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01 tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
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RF1K49157 Test Circuits and Waveforms
(Continued)
tON td(ON) tr VDS RL 90%
tOFF td(OFF) tf 90%
+
RG DUT
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
VGS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
VDS RL
VDD VDS
Qg(TOT)
VGS = 20V VGS
+
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) IG(REF) 0 VGS = 10V
DUT IG(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORM
Soldering Precautions
The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided.
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RF1K49157 PSPICE Electrical Model
SUBCKT RF1K49157 2 1 3 ; CA 12 8 1.834e-9 CB 15 14 1.72e-9 CIN 6 8 1.416e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 34.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRESH 6 21 19 8 1 EZTEMPCO 20 6 18 22 1
LGATE DPLCAP 10 5
rev 3/14/95
LDRAIN DRAIN 2 RLDRAIN DBREAK RDRAIN
ESG + EZTEMPCO 9 RLGATE 20 + 18 22 RGATE 6 GATE 1 6 8 11 16 EVTHRESH + 19 8 21 MOS1 RIN CIN 8 RSOURCE 7 LSOURCE SOURCE 3 RLSOURCE S1A 12 13 8 S1B CA + EGS 6 8 S2A 14 13 13 CB + EDS RVTHRESH 5 8 14 IT 15 S2B 17 RZTEMPCO 19 VBAT + 22 RBREAK 18 EBREAK MOS2 17 18 + DBODY
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 0.237e-9
MOS1 16 6 8 8 MSTRONG M = 0.99 MOS2 16 21 8 8 MWEAK M = 0.01 RBREAK 17 18 RBREAKMOD 1 RDRAIN 5 16 RDRAINMOD 4.39e-3 RGATE 9 20 1.53 RIN 6 8 1e9 RLDRAIN 2 5 1.0 RLGATE 1 9 10.4 RLSOURCE 3 7 0.237 RSOURCE 8 7 RSOURCEMOD 4.44e-3 RTHRESH 22 8 RTHRESMOD 1 RZTEMPCO 18 19 RZTEMPCOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
VBAT 22 19 DC 1 .MODEL DBDMOD D (IS = 1.14e-12 RS = 6.01e-3 TRS1 = 1.05e-4 TRS2 = -2.46e-5 CJO = 2.62e-9 TT = 2.44e-8) .MODEL DBREAKMOD D (RS = 4.89e-1 TRS1 = 2.11e-3 TRS2 = -3.19e-6) .MODEL DPLCAPMOD D (CJO = 1.007e-9 IS = 1e-30 N = 10) .MODEL MSTRONG NMOS (VTO = 2.567 KP = 33.21 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAK NMOS (VTO=2.0225 KP = 33.21 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBREAKMOD RES (TC1 = 9.59e-4 TC2 = -2.87e-7) .MODEL RDRAINMOD RES (TC1 = 8.08e-3 TC2 = 1.6e-5) .MODEL RSOURCEMOD RES (TC1=0 TC2=0) .MODEL RTHRESHMOD RES (TC1=-6.4e-4 TC2=-8.1e-6) .MODEL RZTEMPCOMOD RES (TC1 = -2.43e-3 TC2 = 1.57e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.47 VOFF= -4.47) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.47 VOFF= -6.47) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.3 VOFF= 1.7) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.7 VOFF= -3.3) .ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
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RF1K49157
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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